A Multi–Alphabet Arithmetic Coding Hardware Implementation for Small FPGA Devices
نویسندگان
چکیده
منابع مشابه
A Multi–alphabet Arithmetic Coding Hardware Implementation for Small Fpga Devices
Arithmetic coding is a lossless compression algorithm with variable-length source coding. It is more flexible and efficient than the well-known Huffman coding. In this paper we present a non-adaptive FPGA implementation of a multi-alphabet arithmetic coding with separated statistical model of the data source. The alphabet of the data source is a 256-symbol ASCII character set and does not inclu...
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ژورنال
عنوان ژورنال: Journal of Electrical Engineering
سال: 2013
ISSN: 1335-3632
DOI: 10.2478/jee-2013-0006